This invention relates generally to the field of integrated circuit design and more particularly to integrated circuit cells.
Reduction of quiescent leakage current (xe2x80x9cIDDQxe2x80x9d) in integrated circuits (xe2x80x9cICxe2x80x9d), such as an application specific integrated circuit (xe2x80x9cASICxe2x80x9d), is one goal of integrated circuit design because such a reduction lowers the overall power consumption of the IC. However, implementing features in cells of the IC to reduce the IDDQ also degrades the performance of the cells. Because of the performance degradation, these cells, referred to as xe2x80x9clow power cells,xe2x80x9d are positioned in electrical paths of the IC where the importance of performance is relatively low. Such selective use of low power cells in an IC reduces IDDQ, which lowers the overall power consumption of the IC without sacrificing the overall performance of the IC.
Conventionally, one feature that distinguishes a low power cell from other cells, such as high performance cells, is a larger cell footprint. The footprint is larger because a low power cell has a gate that is longer than the gate of a high performance cell, which requires the contacts of the low power cell to be further apart from each other. Because of the larger footprint, low power cells may not be used in combination with high performance cells in certain ICs. For example, an ASIC, which requires its cells to have a uniform footprint, cannot benefit from the selective use of low power cells.
According to one embodiment of the invention, a method for designing an integrated circuit is provided. The method includes providing a first transistor in a first logic path. The first transistor has a first contact, a first gate length and a first contact to gate centerline spacing. The method also includes providing a second transistor in a second logic path. The second transistor has a second contact, a second gate length and a second contact to gate centerline spacing. The first contact to gate centerline spacing is substantially equal to the second contact to gate centerline spacing. The method also includes selecting a different gate length for the first gate length using a predetermined design criterion.
Some embodiments of the invention provide numerous technical advantages. Some embodiments may benefit from some, none, or all of these advantages. For example, according to one embodiment, an integrated circuit having a combination of high performance and low power cells may be designed or manufactured using a same footprint, which simplifies the design and manufacturing processes. According to another embodiment, an integrated circuit that requires the use of a same cell footprint, such as an application specific integrated circuit, may have a combination of high performance cells and low power cells, which reduces the power consumption level of the integrated circuit. According to another embodiment, the process of switching a high performance to a low power cell, or vice versa, is simplified. According to another embodiment, late substitution of cells during an IC design process made possible.
Other technical advantages may be readily ascertain by one of skill in the art.